| ISBN: ISBN: 0-7803-5092-8
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| ISBN: ISSN: 1089-3539
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| ISBN: DOI: 10.1109/TEST.1998.743181
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| |
| description |
Most built-in self test (BIST) solutions require specialized test
pattern generation hardware which may introduce significant area
overhead and performance degradation. Recently, some authors
proposed test pattern generation on chip by means of functional
units also used in system mode like adders or multipliers. These
schemes generate pseudo-random or pseudo-exhaustive patterns for
serial or parallel BIST. If the circuit under test contains random
pattern resistant faults a deterministic test pattern generator is
necessary to obtain complete fault coverage.
In this paper it is shown that a deterministic test set can be
encoded as initial values of an accumulator based structure, and all
testable faults can be detected within a given test length by
carefully selecting the seeds of the accumulator. A ROM is added for
storing the seeds, and the control logic of the accumulator is
modified. In most cases the size of the ROM is less than the size
required by traditional LFSR-based reseeding approaches.
|
| publisher |
International Test Conference
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| type |
Text
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| Article in Proceedings
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| source |
In: Proceedings of the 29th IEEE International Test Conference
(ITC), Washington, DC, October 1998, pp. 412-421
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| contributor |
Rechnerarchitektur (IFI)
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| subject |
Reliability, Testing, and Fault-Tolerance (CR B.8.1)
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| BIST
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| hardware pattern generator
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| embedded cores
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